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SD56120 RF POWER Transistors, LDMOST plastic family N-Channel enhancement-mode lateral MOSFETs General features Excellent thermal stability Common source configuration Push-pull POUT = 100W with 14dB gain @ 860MHz BeO free package Description The SD56120 is a common source N-Channel enhancement-mode lateral Field-Effect RF power transistor designed for broadband commercial and industrial applications at frequencies up to 1.0GHz. The SD56120 is designed for high gain and broadband performance operating in common source mode at 28 V. It is ideal for broadcast applications from 470 to 860 MHz requiring high linearity. M246 Epoxy sealed Pin connection 1 2 5 4 1-2 Drain 4-5 Gate 3 Source Order codes Part number SD56120 Package M246 Branding TSD56120 July 2006 Rev 3 1/15 www.st.com 15 Contents SD56120 Contents 1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 1.2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 2.2 Static . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Dynamic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 4 5 6 7 Impedances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Typical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2/15 SD56120 Electrical data 1 1.1 Electrical data Maximum ratings Table 1. Symbol V(BR)DSS VGS ID PDISS TJ TSTG Absolute maximum ratings (TCASE = 25C) Parameter Drain-Source Voltage Gate-Source Voltage Drain Current Power Dissipation (@ Tc = 70C) Max. Operating Junction Temperature Storage Temperature Value 65 20 14 217 200 -65 to +150 Unit V V A W C C 1.2 Thermal data Table 2. Symbol RthJC Thermal data Parameter Junction - case thermal resistance Value 0.6 Unit C/W 3/15 Electrical characteristics SD56120 2 Electrical characteristics TCASE = +25 oC 2.1 Static Table 3. Symbol V(BR)DSS IDSS IGSS VGS(Q) VDS(ON) GFS CISS COSS CRSS VGS = 0 V VGS = 0 V VGS = 20 V VDS = 28 V VGS = 10 V VDS = 10 V VGS = 0 V VGS = 0 V VGS = 0 V Static (per section) Test conditions IDS = 1 mA VDS = 28 V VDS = 0 V ID = 200 mA ID = 3 A ID = 3 A VDS = 28 V VDS = 28 V VDS = 28 V f = 1 MHz f = 1 MHz f = 1 MHz 3.0 0.7 3 82 48 2.8 Min 65 1 1 5.0 0.8 Typ Max Unit V A A V V mho pF pF pF Note: REF. 7194566A 2.2 Dynamic Table 4. Symbol POUT GPS D GPS hD IMD Dynamic Test conditions VDD = 28 V IDQ = 400 mA f = 860 MHz Min 100 16 60 16 50 -28 Typ Max Unit W dB % dB % dBt VSWR VDD = 28 V IDQ = 400 mA POUT = 100 W f = 860 MHz 14 VDD = 28 V IDQ = 400 mA POUT = 100 W f = 860 MHz 50 VDD = 28 V IDQ = 400 mA POUT = 100 W PEP VDD = 28 V IDQ = 400 mA POUT = 100 W PEP VDD = 28 V IDQ = 400 mA POUT = 100 W PEP Load VDD = 28 V IDQ = 400 mA POUT = 100 W f = 860 MHz 5:1 mismatch All phase angles Note: f1 = 860 MHz PEP f2 = 860.1 MHz 4/15 SD56120 Impedances 3 Impedances Figure 1. Current conventions Table 5. Impedance data Freq. (MHz) 860 MHz ZIN () 1.11 - j 2.63 ZDL() 3.01 + j 5.34 Note: Measured drain to drain and gate to gate respectively. 5/15 Typical performance SD56120 4 Figure 2. Typical performance Capacitance vs drain voltage (per section) Figure 3. Gate-source voltage vs case temperature C (pF) 1000 f = 1 MHz per section VGS (NORMALIZED) 1.04 1.02 100 Ciss Id = 1 A Id = 2 A Coss 1 Id = 3 A Id = 4 A 10 Id = 5 A 0.98 Crss VDS = 10 V per section 1 0 10 20 30 40 50 0.96 -25 0 25 50 75 100 Vds (V) Tc (C) Figure 4. Id (A) 6 Drain current vs gate voltage Figure 5. Pout (W) 140 120 100 Output power vs input power 5 4 80 3 60 2 40 1 Vds = 10 V per section 20 0 VDD = 28 V IDQ = 400 mA f = 860 MHz 0 2.5 3 3.5 4 4.5 5 0 1 2 3 4 Vgs (V) Pin (W) 6/15 SD56120 Typical performance Figure 6. Pg (dB) 20 19 18 17 Power gain vs input power Figure 7. Nd (%) 70 60 50 40 Efficiency vs output power 16 30 15 14 13 12 0 1 2 3 4 Vdd = 28 V Idq = 400 mA f = 860 MHz 20 10 0 0 20 40 60 80 100 120 140 f = 860 Mhz Vdd = 28 V Idq = 400 mA Pin (W) Pout (W) Figure 8. Power gain vs output power Figure 9. Intermodulation distortion vs output power Gp (dB) 22 Idq = 800 mA Idq = 1 A IMD3 (dBt) 0 -5 20 -10 -15 -20 -25 18 Idq = 400 mA 16 Idq = 200 mA Idq = 600 mA -30 -35 14 -40 -45 f1 = 860 MHz f2 = 860.1 MHz Vdd = 28 V Idq = 400 mA 12 Vdd = 28V f = 860 MHz -50 -55 -60 0 20 10 30 40 50 60 70 80 10 1 10 100 1000 100 90 110 120 Pout (W) Pout (WPEP) 7/15 Typical performance Figure 10. Output power vs drain voltage Pout (W) 130 120 110 115 100 90 80 70 60 105 50 40 30 12 16 20 24 28 32 36 Pin = 2.5 W Idq= 400 mA f = 860 MHz SD56120 Figure 11. Output power vs bias current Pout (W) 120 110 Vdd = 28 V Pin = 2.5 W f = 860 MHz 100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Vds (V) Idq (A) Figure 12. Output power vs gate-source voltage Pout (W) 140 120 100 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 3.5 Vdd = 28 V Pin = 2.5 W f = 860 MHz Vgs (V) 8/15 SD56120 Test circuit 5 Test circuit Figure 13. 860MHz test circuit schematic TL1 Z9 Z3 Z5 Z7 Z6 Z4 Z8 TL2 TRANSMISSON LINE DIMENSIONS Z10 Z11 DIMENSION TABLE IN MM WXL WXL Z1,Z12 0.215 X TYP 5,46 X TYP Z2,Z3 0.215 X 0.850 5,46 X 21,59 Z4,Z5 0.344 X 1.000 8,73 X 25,40 Z6,Z7 0.344 X 0.440 8,73 X 11,17 Z8,Z9 0.700 X 0.870 17,78 X 22,10 Z10,Z11 0.215 X 0.670 5,46 X 17,02 TL1 & TL2 0.100 X 2.37 2,54 X 60,20 DIMENSION OF MCROSTRIP = 1/2 PRINTED BALUN ONLY. DIM Z1 Z12 Z2 VGG FB1 R1 VDD + C16 C28 R2 C29 C22 L1 R3 C21 C20 C19 C18 R7 C6 D.U.T. C12 BALUN1 C2 C3 C9 C4 C5 C8 C10 C11 C13 C14 BALUN2 RF INPUT C1 RF OUTPUT R1 R8 C7 C15 R6 L2 FB2 C27 VGG + C17 R4 R5 VDD C31 C30 C26 C25 C24 C23 Note: 1 2 Dimensions at component symbols are reference for component placement. Gap between ground & transmission line = 0.056 [1.42] +0.002 [0.05] -0.000 [0.00] typ. 9/15 Test circuit SD56120 Table 6. 860MHz test circuit component part list Description .6 - 4.5 pF VARIABLE CAPACITOR .01 F ATC 200B SURFACE MOUNT CERAMIC CHIP CAPACITOR 62 pF ATC 100B SURFACE MOUNT CERAMIC CHIP CAPACITOR 270 pF ATC 100B SURFACE MOUNT CERAMIC CHIP CAPACITOR 1200 pF ATC 700B SURFACE MOUNT CERAMIC CHIP CAPACITOR 0.1 F 500V SURFACE MOUNT CERAMIC CHIP CAPACITOR 10 F 50V ALUMINUM ELECTROLYTIC RADIAL LEAD SURFACE MOUNT CAPACITOR 100 F 63V ALUMINUM ELECTROLYTIC RADIAL LEAD CAPACITOR Component C32 C31, C28 C29, C30 C27, C22 C26, C21 C25 ,C20 C24, C19, C17, C16 C23, C18 C15, C14, C13, C12 47 pF ATC 100B SURFACE MOUNT CERAMIC CHIP CAPACITOR C11 C10 C9, C8 C7, C6, C5 C4 C3, C2 C1 R7, R8 R6, R3 R5, R2 R4, R1 B2, B1 L2, L1 FB2, FB1 PCB 0.8 - 8 pF GIGATRIM VARIABLE CAPACITOR 3.0 pF ATC 100B SURFACE MOUNT CERAMIC CHIP CAPACITOR 4.3 pF ATC 100B SURFACE MOUNT CERAMIC CHIP CAPACITOR 10 pF ATC 100B SURFACE MOUNT CERAMIC CHIP CAPACITOR 2.0 pF ATC 100B SURFACE MOUNT CERAMIC CHIP CAPACITOR 20 pF ATC 100B SURFACE MOUNT CERAMIC CHIP CAPACITOR 1.3 pF ATC 100B SURFACE MOUNT CERAMIC CHIP CAPACITOR 100 OHM 1/4 W SURFACE MOUNT CHIP RESISTOR 22 OHM 1/4 W CARBON LEADED RESISTOR 4.7 OHM 1/4 W CARBON LEADED RESISTOR 82 OHM 1/4 W CARBON LEADED RESISTOR BALUN, 50 OHM SUCOFORM, OD 0.141 2.37 LG COAXIAL CABLE OR EQUIVALENT INDUCTOR, 6 TURN AIR-WOUND #18AWG ID=0.130[3,30] MAGNET WIRE SURFACE MOUNT EMI SHIELD BEAD ULTRALAM 2000. 0.030" THK r = 2.55, 2 Oz ED CU BOTH SIDES 10/15 SD56120 Figure 14. 860MHz production test fixture Test circuit + + + Figure 15. 860MHz test circuit photomaster 6.4 inches 4 inches 11/15 Package mechanical data SD56120 6 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 12/15 SD56120 Table 7. Dim. Min A B C D E F G H I J K L 28.83 16.26 4.19 0.08 1.83 1.40 3.18 5.33 6.48 17.27 5.72 22.86 29.08 16.76 5.08 0.15 2.24 1.65 3.43 1.135 .640 .165 .003 .072 .055 .125 Package mechanical data M246 (.230 x .650 WIDE 4/L BAL N/HERM W/FLG) mechanical data mm. Typ Max 5.59 6.73 18.29 5.97 Min .210 .255 .680 .225 .900 1.145 .660 .200 .006 .088 .065 .135 Inch Typ Max .220 .265 .720 .235 Figure 16. Package dimensions Controlling dimension: Inches Ref. 7145054A 13/15 Revision history SD56120 7 Revision history Table 8. Date 18-Jun-2001 12-Sep-2004 13-Jul-2006 Revision history Revision 1 2 3 First Issue Few updates New template, added lead free info Changes 14/15 SD56120 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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